RISC-V Processor

Verilog + Assembly

To build a 5-stage pipelined processor capable of executing any one array sorting algorithm other than the bubble sort. Basically, you will be converting your single cycle processor to a pipelined one. Normally the instructions you have already implemented should enable you to execute a sorting algorithm program with small additions i.e., you might need to implement the bgt or blt instruction, or something similar, so that you know when you’d need to sdap two values. This would require small modifications to the circuit.